1. Field of the Invention
The present invention relates to a voltage detecting circuit to perform voltage detection by introducing a voltage from a detection node, and to a switching power source apparatus to perform a control operation of a switching element on the basis of the voltage output of the voltage detecting circuit.
2. Related Art
As shown in FIG. 6, there is, for example, a flyback system switching power source apparatus (switching power source apparatus of flyback system) adopting the configuration of detecting a drain-to-source voltage Vds52 of a synchronously rectifying element SW52, made of a power MOS FET or the like, and of performing the on-off control of the synchronously rectifying element SW52 on the basis of the detected voltage Vds52.
In such a switching power source apparatus, as shown in a time chart of FIGS. 7A-7C, when the synchronously rectifying element SW52 is in its off-state (at the time of the low level of the gate voltage Vgs52), the voltage Vds52 at the drain terminal of the synchronously rectifying element SW52 becomes a high voltage composed of an output voltage Vo and an added voltage Vin/N, which is equal to the input voltage Vin divided by a turn ratio N.
Generally, the method of constituting a detection circuit 51 with high-voltage withstanding elements or the method of inputting a dropped voltage into the detection circuit 51 by the use of voltage dividing circuits R51 and R52, as shown in FIG. 6, or by the use of a pull down resistor to perform the voltage detection at a detection point to which the high voltage mentioned above is applied, is used in order to perform the detection.
Japanese Patent Application Laid-Open Publication No. 2004-129364 discloses the circuit to step down an output voltage with a voltage dividing circuit to input the stepped-down voltage into a shunt regulator for generating a reference voltage in order to detect the output voltage.
However, in the case where the voltage Vds52 at the detection node is introduced into the detection circuit 51 through the voltage dividing circuits R51 and R52 as shown in FIG. 6, a detection voltage Vdet50, which is a uniformly divided voltage of the voltage Vds52 from the high range thereof to the low range thereof as shown in FIGS. 7A and 7B, is input into the detection circuit 51 Consequently, in a period T50, in which the voltage Vds52 at the detection node is a low voltage and voltage changes are small, the detection voltage Vdet50, the voltage changes of which are made to be further smaller by the voltage division, is input into the detection circuit 51.
It is supposed here that the detection circuit 51 detects the timing at which the detection voltage Vdet50 reaches a predetermined threshold voltage (for example, a voltage slightly lower than a voltage of zero) Vth in the period T50. In this case, since the voltage changes of the detection voltage Vdet50 become smaller by the voltage dividing circuits R51 and R52, the problem in which the detection accuracy of the timing falls is caused.
Moreover, parasitic capacitance Ca, such as the gate capacitance of a MOS FET, is generated at the input terminal of the detection circuit 51. Consequently, if the voltage dividing circuits R51 and R52 as shown in FIG. 6 exist, a time constant circuit is formed by the resistance R51 and the parasitic capacitance Ca, and consequently the problem of the generation of waveform rounding in the detection voltage Vdet50 by the passage of the voltage Vds52 at the detection node through the time constant circuit is caused. Furthermore, if the voltage drop quantity by the voltage dividing circuits R51 and R52 is made to be larger, then the resistance R51 on the side of the detection node must be the one having a large value. Consequently, even if the parasitic capacitance Ca is that of rather small, the time constant of the time constant circuit becomes a large value. Then, the problem in which, if the waveform rounding is caused in the detection voltage Vdet50, a delay is produced in the detection timing of a voltage is caused.